1. Technical Field
The present invention relates to a vertical semiconductor device and a method of manufacturing the same, and more particularly, to a vertical semiconductor device capable of preventing a floating body effect from occurring and overlapping a vertical gate and a bit line junction region.
2. Related Art
As integration of semiconductor devices is high, dynamic random access memory (DRAM) devices of below 40 nm have been used to improve device integration. However, it is difficult to scale down planar or recess gate transistors below 40 nm, which are used in 8F2 (F: minimum feature size) or 6F2 cell architecture. Therefore, 4F2 cell architecture capable of improving integration one and a half to two times in a given critical dimension has been suggested.
Under 4F2 cell architecture, a source unit and a drain unit of a cell transistor are each required to be a 1F2 size. The source unit becomes coupled to a capacitor storing a carrier, e.g., electric charges, and the drain unit is coupled to a bit line from which the electric charges drain out. Thus, in recent years, study has been made of a vertical cell transistor structure in which the source unit and the drain unit are a 1F2 size. The vertical cell transistor is structured such that a source region and a drain region of a transistor are formed in a vertical direction and the transistor operates along a vertical pillar type channel. That is, compared to the source region and the drain region in a planar transistor in 8F2, a vertical cell transistor structure with a vertically arranged source region and drain region can be formed in a smaller size.
In the 4F2 cell architecture, a bit line junction region is formed in a lower portion of a pillar to be a one side contact (OSC) type.
However, if the bit line junction region is shallow, and thus a gate and the bit line junction region are not overlapped with each other, channel resistance increases and thus, threshold voltage becomes increased and a channel current becomes reduced.
On the other hand, if the bit line junction region is deep, and thus a gate and the bit line junction region overlap, the width of a channel becomes narrow and a floating body phenomenon occurs, isolating the channel region from the substrate by the bit line junction region.